Package structure with dummy die

ABSTRACT

A package structure and method for forming the same are provided. The package structure includes a package component, and a dummy die disposed over the package component. The package structure includes a device die adjacent to the dummy die, and the device die includes a conductive pad, and the conductive pad is electrically connected to the package component.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation application of U.S. patent application Ser. No. 16/396,053, filed on Apr. 26, 2019, now U.S. Pat. No. 10,727,211, which is a Continuation application of U.S. patent application Ser. No. 15/893,109 filed on Feb. 9, 2018, now U.S. Pat. No. 10,276,549, which is a Continuation application of U.S. patent application Ser. No 15/268,843 filed on Sep. 19, 2016, now U.S. Pat. No. 9,922,964, the entire of which is incorporated by reference herein.

BACKGROUND

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic equipment. Semiconductor devices are typically fabricated by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductive layers of material over a semiconductor substrate, and patterning the various material layers using lithography to form circuit components and elements thereon. Many integrated circuits are typically manufactured on a single semiconductor wafer, and individual dies on the wafer are singulated by sawing between the integrated circuits along a scribe line. The individual dies are typically packaged separately, in multi-chip modules, for example, or in other types of packaging.

New packaging technologies, such as package on package (PoP), have begun to be developed, in which a top package with a device die is bonded to a bottom package, with another device die. By adopting the new packaging technologies, various packages with different or similar functions are integrated together.

Although existing package structures and methods of fabricating package structures have generally been adequate for their intended purpose, they have not been entirely satisfactory in all respects.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It should be noted that, in accordance with the standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

FIGS. 1A-1D show cross-sectional representations of various stages of forming a package structure, in accordance with some embodiments of the disclosure.

FIG. 2A shows a top-view of the first device die and the first dummy die, in accordance with some embodiments of the disclosure.

FIG. 2B shows a top-view of the first dummy die covered by the package layer, in accordance with some embodiments of the disclosure.

FIGS. 3A-3G show cross-sectional representations of various stages of forming a package structure, in accordance with some embodiments of the disclosure.

FIGS. 4A-4G show cross-sectional representations of various stages of forming a package structure, in accordance with some embodiments of the disclosure.

FIGS. 5A-5G show cross-sectional representations of various stages of forming a package structure, in accordance with some embodiments of the disclosure.

FIGS. 6A-6B show cross-sectional representations of various stages of forming a package structure, in accordance with some embodiments of the disclosure.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, or examples, for implementing different features of the subject matter provided. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. In addition, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Some variations of the embodiments are described. Throughout the various views and illustrative embodiments, like reference numbers are used to designate like elements. It should be understood that additional operations can be provided before, during, and after the method, and some of the operations described can be replaced or eliminated for other embodiments of the method.

Embodiments for a package structure and method for forming the same are provided. FIGS. 1A-1D show cross-sectional representations of various stages of forming a package structure 100, in accordance with some embodiments of the disclosure.

As shown in FIG. 1A, a substrate 102 is provided. The substrate 102 may be made of silicon (Si) or other semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide. The substrate 102 is a temporary support substrate. In some embodiments, the substrate 102 is made of semiconductor material, ceramic material, polymer material, metal material, another applicable material or a combination thereof. In some embodiments, the substrate 102 is a glass substrate. In some embodiments, the substrate 102 is a semiconductor substrate, such as silicon wafer.

A dielectric layer 106 is formed on the substrate 102. In some embodiments, the dielectric layer 106 is made of polymer or a polymer-containing layer. The dielectric layer 106 may be a poly-p-phenylenebenzobisthiazole (PBO) layer, a polyimide (PI) layer, a solder resist (SR) layer, an Ajinomoto buildup film (ABF), a die attach film (DAF), another applicable material, or a combination thereof.

A first device die 140 and a first dummy die 160 are formed on the dielectric layer 106 by using an adhesive layer 108 as an adhesion glue. The adhesive layer 108 includes any suitable adhesive material, such as a polymer material. In some embodiments, the adhesive layer 108 includes a double sided adhesive tape. The adhesive layer 108 is formed using a lamination process, a spin coating process, or another suitable process.

The first device die 140 includes a semiconductor substrate 142, a dielectric layer 144, a conductive pad 146, a passivation layer 148 and a connector 150. The conductive pad 146 is electrically connected to the connector 150. In some embodiments, the dielectric layer 144 is made of silicon oxide, silicon oxynitride, borosilicate glass (BSG), phosphoric silicate glass (PSG), borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), low-k material, porous dielectric material, or a combination thereof. In some embodiments, the dielectric layer 144 is formed by a chemical vapor deposition (CVD) process, a spin-on process, a sputtering process, or a combination thereof.

In some embodiments, the passivation layer 148 is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some other embodiments, the passivation layer 148 is made of polymer. In some embodiments, the passivation layer 148 is formed by a chemical vapor deposition (CVD) process, a spin-on process, a sputtering process, or a combination thereof.

Other device elements may be formed in the first device die 140. The device elements include transistors (e.g., metal oxide semiconductor field effect transistors (MOSFET), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors (BJT), high-voltage transistors, high-frequency transistors, p-channel and/or n channel field effect transistors (PFETs/NFETs), etc.), diodes, and/or other applicable elements. Various processes are performed to form device elements, such as deposition, etching, implantation, photolithography, annealing, and/or other applicable processes.

The first dummy die 160 includes a substrate 162. The substrate 162 may be made of silicon (Si) or other semiconductor materials, such as germanium (Ge). In some embodiments, the substrate 102 is made of a compound semiconductor such as silicon carbide, gallium arsenic, indium arsenide, or indium phosphide.

The first dummy die 160 does not provide any function, and no connectors are formed on the top of the first dummy die 160. The first dummy die 160 is used to reduce the asymmetric warpage (in X- and Y-direction) or bending stress on the substrate 102. The coefficient of thermal expansion (CTE) of the first dummy die 160 is substantially identical to or similar to the coefficient of thermal expansion (CTE) of the first device die 140. In some embodiments, the first dummy die 160 is made of silicon. If the coefficient of thermal expansion (CTE) of the first dummy die 160 differs significantly from that of the first device die 140, the first dummy die 160 may not compensate for the stress. Therefore, the asymmetric warpage in wafer level package level or package (PKG) level may occur and resulted in yield loss during wafer level process and PKG joint process.

The top surface of the first device die 140 is higher than the top surface of the first dummy die 160. More specifically, a top surface of the passivation layer 148 is higher than the top surface of the first dummy die 160. The first device die 140 has a first height H₁ in a Z-direction, and the first dummy die 160 has a second height H₂ in a Z-direction (the Z-direction is perpendicular to a top surface of the substrate 102). The second height H₂ is smaller than the first height H₁. In some embodiments, a height ratio of the second height H₂ to the first height H₁ is in a range from about 65% to about 85%. If the ratio is greater than 85%, the risky level of cracks forming in the redistribution structure formed above the interface between the first dummy die 160 and a package layer (formed later) may become serious. If the ratio is smaller than 65%, the suppression of asymmetric warpage may not be significant.

After the first device die 140 and a first dummy die 160 are formed, a package layer 170 is formed between the first device die 140 and the first dummy die 160, as shown in FIG. 1B, in accordance with some embodiments of the disclosure. In other words, the first device die 140 and the first dummy die 160 are surrounded by the package layer 170.

In some embodiments, the package layer 170 is made of a molding compound, such as liquid epoxy, deformable gel, silicon rubber, or the like. In some embodiments, the molding compound is dispensed over the first device die 140 and a first dummy die 160, and therefore a thermal process is performed to harden the molding compound. A planarizing process is performed to expose the top surface of the connector 150. After the planarizing process, the top surface of the first device die 140 is substantially leveled with that of the package layer 170. In some embodiments, the planarizing process includes grinding process, a chemical mechanical polishing (CMP) process, an etching process, another applicable process or a combination thereof.

Afterwards, a redistribution structure 180 is formed on the package layer 170, the first device die 140 and the first dummy die 160, as shown in FIG. 1C, in accordance with some embodiments of the disclosure. The redistribution structure 180 includes one or more redistribution lines (RDL) and one or more passivation layers. The redistribution structure 180 includes the redistribution lines (RDL) 184 formed in the passivation layer 182.

In some embodiments, the redistribution lines (RDL) 184 are made of metal materials, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy. In some embodiments, the RDL 184 is formed by plating, electroless plating, sputtering or chemical vapor deposition (CVD). In some embodiments, the passivation layer 182 is made of organic materials, such as polybenzoxazole (PBO), benzocyclobutene (BCB), polyimides (PI), silicone, acrylates, siloxane, or a combination thereof. In some other embodiments, the passivation layer 182 is made of non-organic materials, such as silicon oxide, un-doped silicate glass, silicon oxynitride, solder resist (SR), silicon nitride, HMDS (hexamethyldisilazane).

Afterwards, a top passivation layer 186 is formed on the redistribution lines (RDL) 184, as shown in FIG. 1D, in accordance with some embodiments of the disclosure. In some embodiments, the top passivation layer 186 is made of organic materials, such as polybenzoxazole (PBO), benzocyclobutene (BCB), polyimide (PI), silicone, acrylates, siloxane, or a combination thereof. In some other embodiments, the top passivation layer 186 is made of non-organic materials, such as silicon oxide, un-doped silicate glass, silicon oxynitride, solder resist (SR), silicon nitride, HMDS (hexamethyldisilazane).

An under bump metallurgy (UBM) layer 188 is formed in the passivation layer 186, and an electrical connector 190 is formed on the UBM layer 188. The electrical connector 190 is electrically connected to the redistribution lines (RDL) 184. Therefore, the package structure 100 is obtained.

After the package structure 100 is formed, a reliability test is performed on the package structure 100 to confirm the function of the package structure 100 to predict mean-time to failure (MTFF) of package structure 100. The reliability test includes a thermal-cycle process. When the package structure 100 is under the thermal-cycle process, the package layer 170 and the first device die 140 may expand at different rates since the package layer 170, the first device die 140 and the first dummy die 160 each have different coefficients of thermal expansion (CTE). Therefore, the stress is concentrated on the interface between the package layer 170 and the first device die 140. As a result, the redistribution lines (RDL) 184 directly above the interface between the package layer 170 and the first device die 140 may crack due to the concentration of stress. The cracking phenomenon will become serious especially at portions of the redistribution lines (RDL) 184 which are directly over the corners of the first device die 140. When the second height (H₂) equals to that of the first device die (H₁), the cracking phenomenon will appear on the first dummy die 160).

In order to prevent cracking, the first dummy die 160 with a smaller height H₂ is formed adjacent to the first device die 140. The interface between the first dummy die 160 and the package layer 170 is relatively far away from the redistribution lines (RDL) 184 to reduce cracking risk, compared with the first dummy die 160 having a height that is the same as the first device die 140.

In some embodiments, a height ratio of the second height H₂ to the first height H₁ is in a range from about 65% to about 85%. If the ratio is greater than 85%, the problem of cracking may become serious. If the ratio is less than 65%, warpage may occur.

FIG. 2A shows a top-view of the first device die 140 and the first dummy die 160, in accordance with some embodiments of the disclosure. FIG. 1A shows a cross-sectional representation along line I-I′ shown in FIG. 2A.

As shown in FIG. 2A, the first device die 140, the first dummy die 160 and the third device die 165 are formed on the substrate 102. The top-view shape of the first dummy die 160 may be a rectangle, square, circle, or the like. The top-view shape of the first dummy die 160 depends on the top-view shape of the first device die 140 and the third device die 165. If no dummy die is present on the substrate 102 and adjacent to the first device die 140 and the third device die 165, the stresses in the X-direction are not equal to the stresses in the Y-direction. Therefore, when the package structure 100 is under thermal-cycle process (the cycle of high temperature and the low temperature), asymmetric warpage or bending problems may occur due to the unequal distribution of stresses.

The first function of the first dummy die 160 is to balance the distribution of stress to prevent asymmetric warpage in wafer level package or package (PKG) level. In addition, the bending stress on the substrate 102 is also decreased by using the first dummy die 160 due to less volume of the package layer 170, which has large CTE. The second function of the first dummy die 160 with less height (H₂) than the first height of first device die 140 (H₁) is to reduce the risk of cracking in the redistribution lines (RDL) 184 which are directly above the interface between the first dummy die 160 and the package layer 170.

In some embodiments, the spacing distance d₁ between the first device 140 and the first dummy die 160 is in a range from about 50 μm to about 100 μm. If the spacing distance d₁ is greater than 100 μm, the die to die (D2D) talking distance becomes longer and results in significant signal delay at high operating frequency. If the spacing distance d₁ is less than 50 μm, the control of the accuracy of die placement process becomes a challenge.

FIG. 2B shows a top-view of the first dummy die 160 covered by the package layer 170, in accordance with some embodiments of the disclosure. FIG. 1B shows a cross-sectional representation along line II-II′ shown in FIG. 2B.

As shown in FIG. 2B, the first dummy die 160 is covered by the package layer 170, and therefore a top surface of the first device die 140 and a top surface of the third device die 165 are exposed.

A Keep-Out Zone (KOZ) is a region defined around the dies (e.g., 140,160) where no other devices can be placed within. The RDL lines 184 of the redistribution structure 180 directly above the KOZ regions may easily crack because of the stress concentrated on the KOZ regions. During fabricating the package structure 100, some thermal process may perform on the first device die 140, the first dummy die 160 and the package layer 170. The package layer 170 and the first device die 140 may expand at different rates since the package layer 170, the first device die 140 and the first dummy die 160 each have different coefficients of thermal expansion (CTE). As a result, the stresses are concentrated on the KOZ regions where are close to the first device die 140. If the first dummy die 160 and the first device die 140 have the same height, there are twelve KOZ regions (every die has four KOZ corners). However, as shown in FIG. 2B, since the first dummy die 160 with a lower height is covered by the package layer 170, there are eight Keep-Out Zone (KOZ) regions (the circle region A), rather than twelve Keep-Out Zone (KOZ) regions. Therefore, when the number of the KOZ regions is reduced, the problem of cracking of the RDL lines 184 of the redistribution structure 180 is reduced.

FIGS. 3A-3G show cross-sectional representations of various stages of forming a package structure 200, in accordance with some embodiments of the disclosure.

As shown in FIG. 3A, a release layer 104 is formed on a carrier substrate 103. The carrier substrate 103 is configured to provide temporary mechanical and structural support during subsequent processing steps. In some embodiments, the carrier substrate 103 includes glass, silicon oxide, aluminum oxide, a combination thereof, and/or the like, in accordance with some embodiments. In some other embodiments, the carrier substrate 103 includes a wafer.

The release layer 104 may be made of glue, or may be a lamination material, such as a foil. In some embodiments, the release layer 104 is photosensitive and is easily detached from the carrier substrate 103 by light irradiation. For example, ultra-violet (UV) light or laser light is used to detach the release layer 104. In some embodiments, the release layer 104 is a light-to-heat-conversion (LTHC) coating. In some other embodiments, the release layer 104 is heat-sensitive and is easily detached from the carrier substrate 103 when it is exposed to heat.

The dielectric layer 106 is formed on the release layer 104. The dielectric layer 106 is made of polymer or a polymer-containing layer. The dielectric layer 106 may be a poly-p-phenylenebenzobisthiazole (PBO) layer, a polyimide (PI) layer, a solder resist (SR) layer, an Ajinomoto buildup film (ABF), a die attach film (DAF), another applicable material, or a combination thereof.

A seed layer 112 is formed over the dielectric layer 106. Afterwards, a mask layer (not shown) is formed on the seed layer 112, and opening is formed in the mask layer to expose the seed layer 112. Afterwards, a conductive structure 114 is formed in the opening. As a result, the conductive structure 114 is formed on the seed layer 112. The conductive structure 114 and the seed layer 108 are in combination referred to as through InFO vias (TIV) 116, which are also referred to as through vias 116. In some embodiments, the conductive structure 114 and the seed layer 112 are made of the same material, and therefore there is no distinguishable interface therebetween. In some embodiments, the through vias 116 have a third height H₃ in the Z-direction.

In some embodiments, the seed layer 112 is made of metal material, such as copper (Cu), titanium (Ti), copper alloy, titanium alloy, or a combination thereof. In some embodiments, the seed layer 112 is formed by a deposition process, such as a chemical vapor deposition process (CVD), physical vapor deposition process (PVD), another applicable process, or a combination thereof. The conductive structure 114 may be made of metal material, such as copper (Cu), aluminum (Al), tungsten (W), nickel (Ni), an alloy thereof, or a combination thereof. In some embodiments, the conductive structure 114 is formed by a plating process.

After the through vias 116 are formed, the first device die 140 and the first dummy die 160 are formed on the dielectric layer 106 by using the adhesive layer 108 as the adhesive glue, as shown in FIG. 3B, in accordance with some embodiments of the disclosure. In some embodiments, the adhesive layer 108 is die attach film (DAF).

It should be noted that the first device die 140 has a first height H₁, and the first dummy die 160 has a second height H₂. The first height H₁ is greater than the second height H₂. The third height H₃ is greater than the first height H₁. In some embodiments, a height ratio of the second height H₂ to the first height H₁ is in a range from about 65% to about 85%. If the ratio is greater than 85%, the problem of cracks forming in the redistribution structure formed above the interface between package layer 170 (formed later) and first device die 140 may become serious. If the ratio is smaller than 65%, warpage may occur.

Afterwards, the package layer 170 is formed over the first device die 140 and the first dummy die 160. In some embodiments, the package layer 170 completely encapsulates and covers the first device die 140, the first dummy die 160, and the through vias (TIVs) 116. The package layer 170 is in direct contact with the first dummy die 160. Afterwards, a planarizing process is performed on the package layer 170 to expose the top surface of the first device die 140 and the top surface of the through vias 116, as shown in FIG. 3C, in accordance with some embodiments of the disclosure.

It should be noted that the first dummy die 160 is covered by the package layer 170. The top surface and the sidewalls of the first dummy die 160 is surrounded or encapsulated by the package layer 170, and only the bottom surface of the first dummy die 160 is not in contact with the package layer 170.

In some embodiments, the package layer 170 is made of a molding compound, such as liquid epoxy, deformable gel, silicon rubber, or the like. In some embodiments, the molding compound is dispensed over the dielectric layer 106, the first device die 140 and the first dummy die 160 and therefore a thermal process is performed to harden the molding compound. After the planarizing process, the top surface of the first device die 140 is substantially level with that of the through vias 116. In some embodiments, the planarizing process includes a grinding process, a chemical mechanical polishing (CMP) process, an etching process, another applicable process, or a combination thereof.

Afterwards, the redistribution structure 180 is formed on the package layer 170, the first device die 140 and the first dummy die 160, as shown in FIG. 3D, in accordance with some embodiments of the disclosure. The redistribution structure 180 includes one or more redistribution lines (RDL) and one or more passivation layers. The redistribution structure 180 includes the redistribution lines (RDL) 184 formed in the passivation layer 182.

Afterwards, the passivation layer 186 is formed on the redistribution lines (RDL) 184, as shown in FIG. 3E, in accordance with some embodiments of the disclosure. The under bump metallurgy (UBM) layer 188 is formed in the passivation layer 186, and the electrical connector 190 is formed on the UBM layer 188. The electrical connector 190 is electrically connected to the redistribution lines (RDL) 184. Therefore, the package structure 200 is obtained. In some embodiments, the package structure 200 is a fan-out wafer level package structure. The fan-out wafer level package means that the I/O pads on the die structure can be distributed to a greater area than the die structure, and hence the number of I/O pads on the surface of the die structure can be increased.

After the electrical connector 190 is formed, and the carrier substrate 103 and the release layer 104 are removed, as shown in FIG. 3F, in accordance with some embodiments of the disclosure. Afterwards, the electrical connector 190 is attached to a carrier 192. The carrier substrate 103 is removed by projecting a UV light or a laser on the release layer 104, such that the release layer 104 is decomposed. The carrier 192 includes a tape which is photosensitive or heat-sensitive and is easily detached from the electrical connector 190.

Afterwards, a portion of the dielectric layer 106 is removed to form openings 194. In some embodiments, the seed layer 108 is not removed or completely removed. In some other embodiments, a portion of the seed layer 108 is removed, and the remaining seed layer 108 is exposed. In some other embodiments, the opening 194 is formed by a laser drilling process, an etching process, or another applicable process.

After the opening 194 is formed, an electrical connector 196 is filled into the opening 194, as shown in FIG. 3G, in accordance with some embodiments of the disclosure. Afterwards, the top package 300 is bonded to the package structure 200 by the electrical connector 196. Before the electrical connector 196 is filled into the opening 194, a solder paste (not shown) is pre-formed in the opening 194 by a print or jetting process.

The top package 300 includes a package substrate 302 and device dies 310. The bonding of the device dies 310 to the package substrate 302 may be achieved through wire-bonding, flip-chip bonding or the like. In some embodiments, the device dies 310 includes memory dies, such as Static Random Access Memory (SRAM) die, Dynamic Random Access Memory (DRAM) die or the like.

Afterwards, the package structure 200 may continue to undergo other processes to form other structures or devices. Afterwards, a dicing process is performed to separate the structure into chip packages.

In some embodiments, the CTE of the package layer 170 is higher than the CTE of the first dummy die 160, and the CTE of the first dummy die 160 is similar to the CTE of the first device die 140. For example, the CTE of the package layer 170 made of molding compound is in a range from about 5 ppm/° C.- to 10 ppm/° C. before glass transition temperature (Tg), and the CTE of the first dummy die 160 made of silicon die is in a range from about 2.5 ppm/° C. to about 3.5 ppm/° C. before Tg. The stress may concentrate on the interface between the first dummy die 160 and the package layer 170 due to the mismatch of the CTE. Therefore, when the top surface of the first dummy die 160 is lower than the top surface of the first device die 140, the interface of the first dummy die 160 and the package layer 170 is far away from the first metal layer (M1) of the redistribution lines (RDL) 184 of the redistribution structure 180. Cracking of the redistribution lines (RDL) 184 of the redistribution structure 180 may be reduced, and the performance of the package structure 200 is improved.

FIGS. 4A-4G show cross-sectional representations of various stages of forming a package structure 400, in accordance with some embodiments of the disclosure. Some processes and materials used to form the package structure 400 are similar to, or the same as, those used to form package structure 200 and are not repeated herein.

As shown in FIG. 4A, the release layer 104 is formed on the carrier substrate 103. In some embodiments, the carrier substrate 103 includes glass, silicon oxide, aluminum oxide, a combination thereof, and/or the like, in accordance with some embodiments. In some other embodiments, the carrier substrate 103 includes a wafer.

The dielectric layer 106 is formed on the release layer 104. The through vias 116 are formed on the dielectric layer 106. The through vias 116 are made of conductive materials.

Afterwards, the first device die 140 and the first dummy die 160 are formed on the dielectric layer 106 by the adhesive layer 108, as shown in FIG. 4B, in accordance with some embodiments of the disclosure. The first dummy die 160 includes the substrate 162 and a buffer layer 164.

The buffer layer 164 is used to protect the substrate 162 from being damaged or cracked during thinning process. In some embodiments, the buffer layer 164 is made of polymer, such as poly-p-phenylenebenzobisthiazole (PBO) or polyimide (PI). In some other embodiments, the buffer layer 164 is made of silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In some embodiments, the buffer layer 164 and the passivation layer 148 are made of the same materials.

It should be noted that the first device die 140 has a first height H₁, and the first dummy die 160 has a second height H₂. The second height H₂ is smaller than the first height H₁ to reduce the cracking of the RDL lines 184 which are directly above the interface between the package layer 170 and the first dummy die 160.

After the first device die 140 and the first dummy die 160 are formed, the package layer 170 is formed between the first device die 140 and the first dummy die 160, as shown in FIG. 4C, in accordance with some embodiments of the disclosure. In other words, the first device die 140 and the first dummy die 160 are surrounded by the package layer 170.

Afterwards, the redistribution structure 180 is formed on the package layer 170, the first device die 140 and a first dummy die 160, as shown in FIG. 4D, in accordance with some embodiments of the disclosure. The redistribution structure 180 includes one or more redistribution lines (RDL) and one or more passivation layers. The redistribution structure 180 includes the redistribution lines (RDL) 184 formed in the passivation layer 182.

Afterwards, the passivation layer 186 is formed on the redistribution lines (RDL) 184, as shown in FIG. 4E, in accordance with some embodiments of the disclosure. The under bump metallurgy (UBM) layer 188 is formed in the passivation layer 186, and the electrical connector 190 is formed on the UBM layer 188. The electrical connector 190 is electrically connected to the redistribution lines (RDL) 184. Therefore, the package structure 400 is obtained.

After the electrical connector 190 is formed, the carrier substrate 103 and the release layer 104 are removed, as shown in FIG. 4F, in accordance with some embodiments of the disclosure. Afterwards, the electrical connector 190 is attached to a carrier 192. Afterwards, a portion of the dielectric layer 106 is removed to form openings 194.

After the opening 194 is formed, the electrical connector 196 is filled into the opening 194, as shown in FIG. 4G, in accordance with some embodiments of the disclosure. Afterwards, the top package 300 is bonded to the package structure 400 by the electrical connector 196. The top package 300 includes a package substrate 302 and device dies 310.

It should be noted that the buffer layer 164 is formed on the substrate 162 to protect the substrate 162 from being damaged, especially when the substrate 162 has a smaller height. The top surface of the buffer layer 164 is still lower than the top surface of the first device die 140. Therefore, the problem of the redistribution structure cracking is reduced.

FIGS. 5A-5G show cross-sectional representations of various stages of forming a package structure 500, in accordance with some embodiments of the disclosure. Some processes and materials used to form the package structure 500 are similar to, or the same as, those used to form package structure 200 and are not repeated herein.

As shown in FIG. 5A, the release layer 104 is formed on the carrier substrate 103. The dielectric layer 106 is formed on the release layer 104. A backside redistribution structure 107 is formed on the dielectric layer 106. The backside redistribution structure 107 includes one or more redistribution lines (RDL) and one or more passivation layers. The redistribution structure 107 includes the redistribution lines (RDL) formed in the passivation layer. In some embodiments, the redistribution lines (RDL) are made of metal materials, such as copper (Cu), copper alloy, aluminum (Al), aluminum alloy, tungsten (W), tungsten alloy, titanium (Ti), titanium alloy, tantalum (Ta), or tantalum alloy.

The through vias 116 are formed on the redistribution structure 107. The through vias 116 are made of conductive materials. The through vias 116 are electrically connected to the redistribution structure 107.

Afterwards, the first device die 140 and the first dummy die 160 are formed on redistribution structure 107 106 by the adhesive layer 108, as shown in FIG. 5B, in accordance with some embodiments of the disclosure. The first dummy die 160 includes the substrate 162. In some other embodiments, a buffer layer is formed on the substrate 162.

Afterwards, the package layer 170 surrounds the first device die 140 and the first dummy die 160, as shown in FIG. 5C, in accordance with some embodiments of the disclosure.

Afterwards, the redistribution structure 180 is formed on the package layer 170, the first device die 140 and a first dummy die 160, as shown in FIG. 5D, in accordance with some embodiments of the disclosure. The redistribution structure 180 includes the redistribution lines (RDL) 184 formed in the passivation layer 182.

Afterwards, the passivation layer 186 is formed on the redistribution lines (RDL) 184, as shown in FIG. 5E, in accordance with some embodiments of the disclosure. The UBM layer 188 is formed in the passivation layer 186, and the electrical connector 190 is formed on the UBM layer 188. Therefore, the package structure 500 is obtained.

After the electrical connector 190 is formed, the carrier substrate 103 and the release layer 104 are removed, as shown in FIG. 5F, in accordance with some embodiments of the disclosure. Afterwards, the electrical connector 190 is attached to a carrier 192. Afterwards, a portion of the dielectric layer 106 is removed to form openings 194. The metal layer of the backside redistribution structure 107 is exposed by the opening 194.

After the opening 194 is formed, an electrical connector 196 is filled into the opening 194, as shown in FIG. 5G, in accordance with some embodiments of the disclosure. Afterwards, the top package 300 is bonded to the package structure 500 by the electrical connector 196. The top package 300 includes a package substrate 302 and device dies 310.

FIGS. 6A-6B show cross-sectional representations of various stages of forming a package structure 600, in accordance with some embodiments of the disclosure. Some processes and materials used to form the package structure 600 are similar to, or the same as, those used to form package structure 200 and are not repeated herein.

As shown in FIG. 6A, the first device die 140 and the first dummy die 160 are formed on the dielectric layer 106. The through vias 116 are formed on the dielectric layer 106. The first device die 140, the first dummy die 160 and the through vias 116 are encapsulated by the package layer 170.

The redistribution structure 180 is formed on the package layer 170. A second dummy die 660 and a second device die 640 are formed on the redistribution structure 180. The second through vias 616 are formed on the redistribution structure 180. The dummy die 660, the second device die 640, and the second through vias 616 are encapsulated by the second package layer 670. The second dummy die 660 is directly above the first device die 140, and the second device die 640 is directly above the first dummy die 160 to prevent the asymmetric warpage of the package structure 600.

The second redistribution structure 680 is formed on the second package layer 670. The second redistribution structure 680 includes redistribution lines (RDL) 684 formed in the passivation layer 682. The passivation layer 686 is formed on the redistribution lines (RDL) 684. The UBM layer 688 is formed in the passivation layer 686, and the electrical connector 690 is formed on the UBM layer 688.

Afterwards, the electrical connector 690 is attached to a carrier (not shown). Afterwards, a portion of the dielectric layer 106 is removed to form openings 194. The bottom surface of the through vias 116 is exposed by the opening 194.

After the opening 194 is formed, an electrical connector 196 is filled into the opening 194, as shown in FIG. 6B, in accordance with some embodiments of the disclosure. Afterwards, the top package 300 is bonded to the package structure 600 by the electrical connector 196. The top package 300 includes a package substrate 302 and device dies 310.

Embodiments for forming a package structure and method for forming the same are provided. A dummy die and a device die are formed on a substrate, and the dummy die and the device die are encapsulated by a package layer. A redistribution structure is formed on the package layer. The device die has a first height, and the dummy die has a second height. The second height is smaller than the first height. As a result, the interface between the dummy die and the package layer is away from the redistribution structure. Therefore, the problem of the redistribution structure cracking is reduced, and the performance of the package structure is improved.

In some embodiments, a package structure is provided. The package structure includes a device die, and a through via formed adjacent to the device die, wherein the through via has a first height. The package structure also includes a dummy die adjacent to the device die, wherein the dummy die has a second height smaller than the first height

In some embodiments, a package structure is provided. The package structure includes a first package structure and a second package structure. The first package structure comprises a first package layer, a first device die formed in the first package layer, a first dummy die formed in the first package layer, and the first dummy die has a height which is smaller than a thickness of the first package layer. The first package structure further comprises an electrical connector formed below the first dummy die, and a second package structure formed below the first package structure. The second package structure comprises a second device die, and the electrical connector is between the first device die and the second device die.

In some embodiments, a package structure is provided. The package structure includes a dielectric layer, a first dummy die formed on the dielectric layer, and the first dummy die has a first surface and a second surface, and the first surface of the first dummy die faces the dielectric layer. The package structure further includes a first package layer surrounding the first dummy die, and the first package layer is in direct contact with the second surface of the first dummy die. The package structure includes a second dummy die formed on the second surface of the dielectric layer, and a second package layer surrounding the second dummy die. A bottom surface of the second dummy die is covered by the second package layer.

In some embodiments, a package structure is provided. The package structure includes a package component, and a dummy die disposed over the package component. The package structure includes a device die adjacent to the dummy die, and the device die comprises a conductive pad, and the conductive pad is electrically connected to the package component.

In some embodiments, a package structure is provided. The package structure includes a first package component, a second package component formed over the first package component. The package structure also includes a first memory die between the first package component and the second package component, an a first dummy die adjacent to the first memory die. A bottom surface of the first dummy die is higher than a bottom surface of the first memory die, and the first dummy die is embedded in a package layer.

In some embodiments, a package structure is provided. The package structure includes a first package component, and a first device die formed on a top surface of the first package component. The package structure includes a first dummy die formed on the top surface of the first package component, and the first device die has a first thickness greater than a second thickness of the first dummy die. The package structure also includes a second dummy die formed below a bottom surface of the first package component, and the first dummy die is not aligned with the second dummy die.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure. 

What is claimed is:
 1. A package structure, comprising: a package component; a dummy die disposed over the package component; a device die adjacent to the dummy die, wherein the device die comprises a conductive pad, and the conductive pad is electrically connected to the package component; and a buffer layer formed below the dummy die, wherein the buffer layer has a first surface and an opposite second surface, the first surface is in direct contact with a bottom surface of the dummy die and the second surface is in direct contact with a package layer.
 2. The package structure as claimed in claim 1 a sidewall surface of the dummy die is in direct contact with the package layer.
 3. The package structure as claimed in claim 1, wherein the device die comprises a memory die, and the memory die comprises a Static Random Access Memory (SRAM) die or a Dynamic Random Access Memory (DRAM) die.
 4. The package structure as claimed in claim 1, further comprising: a through via formed adjacent to the device die, wherein a height of the through via is greater than a height of the dummy die.
 5. The package structure as claimed in claim 1, wherein the device die has a first height, and the dummy die has a second height, and a height ratio of the second height to the first height is in a range from about 65% to about 85%.
 6. The package structure as claimed in claim 1, further comprising: a second package structure formed over the device die and the dummy die.
 7. The package structure as claimed in claim 6, further comprising: an adhesion layer formed on a top surface of the dummy die, wherein the adhesion layer is between the second package structure and the dummy die.
 8. A package structure, comprising: a first package component; a second package component formed over the first package component; a first memory die between the first package component and the second package component; and a first dummy die adjacent to the first memory die, wherein a bottom surface of the first dummy die is higher than a bottom surface of the first memory die, and the first dummy die is embedded in a package layer, and a height of the first dummy die is smaller than a height of the first memory die.
 9. The package structure as claimed in claim 8, wherein the bottom surface and sidewall surfaces of the first dummy die are in direct contact with the package layer.
 10. The package structure as claimed in claim 8, further comprising: a through via formed adjacent to the first dummy die, wherein a height of the through via is greater than a height of the first dummy die.
 11. The package structure as claimed in claim 8, further comprising: a first redistribution structure formed on the first memory die and the first dummy die, wherein the first redistribution structure is electrically connected to the first memory die.
 12. The package structure as claimed in claim 8, wherein the memory die comprises a conductive pad, and a bottom surface of the first dummy die is higher than a top surface of the conductive pad.
 13. A package structure, comprising: a first package component; a first device die formed on a top surface of the first package component; a first dummy die formed on the top surface of the first package component, wherein the first device die has a first thickness greater than a second thickness of the first dummy die; and a second dummy die formed below a bottom surface of the first package component, wherein the first dummy die is not aligned with the second dummy die, wherein the second dummy die is directly below the first device die, and a height of the second dummy die is smaller than a height of the first device die.
 14. The package structure as claimed in claim 13, further comprising: a second device die adjacent to the second dummy die, wherein the second device die is directly below the first dummy die.
 15. The package structure as claimed in claim 13, further comprising: a second package component formed over the first device die and the first dummy die.
 16. The package structure as claimed in claim 15, further comprising: a third package component formed below the second dummy die.
 17. The package structure as claimed in claim 13, wherein the first device die comprises a conductive pad, and a top surface of the first dummy die is lower than a top surface of the conductive pad.
 18. The package structure as claimed in claim 13, wherein the first device die comprises a memory die, and the memory die comprises a Static Random Access Memory (SRAM) die or a Dynamic Random Access Memory (DRAM) die.
 19. The package structure as claimed in claim 1, further comprising: a through via formed adjacent to the device die, wherein a top surface of the through via is leveled with a top surface of the device die.
 20. The package structure as claimed in claim 13, further comprising: a third die formed below the second dummy die, wherein the second dummy die is covered by a first package layer, and the third die is covered by a second package layer, and the first package layer is separated from the second package layer. 